This invention relates to electronic data-processing systems and, more particularly, to improving latency in a real-time operating environment.
Some computer and data processing applications demand real-time response from the computer system. For example, telecommunication and data-communication applications often involve real-time processing of network data as a result of multimedia, audio, and video applications and user-data. The real-time demand often places stringent requirements on the hardware, software, or both.
To address the demands of real-time applications, designers employ sophisticated system designs with correspondingly complex hardware and software components. Complex hardware designs typically include high levels of integration and reside on a large silicon die, for example, within programmable gate-arrays (PGAs), field-programmable gate arrays (FPGAs), programmable logic-devices (PLDs), or complex programmable logic-devices (CPLDs).
Providing a high-performance system with good real-time response entails designing sophisticated software (both embedded software and the development tools accompanying the data-processing system) and high-speed hardware circuitry. Designing a system with still higher performance requires optimized layout of the circuitry on the silicon die. Thus, an optimal system design includes an appropriate mix of the three performance factors, i.e., hardware performance, software performance, and silicon layout. Focusing on any one of these factors may create a partly optimized system, but not an optimal overall solution. Worse yet, failing to provide an optimal silicon layout may negate the advantages of optimized hardware, software, or both. Unfortunately, no comprehensive design approach exists that provides an optimal mix of software performance, hardware performance, and silicon-layout performance.
Another aspect of high-performance data-processing systems relates to the execution of instructions within the processor circuitry. Software instructions that operate on data present within the processor (e.g., within the processor""s internal registers) often execute at high speeds, i.e., with low latency. On the other hand, software instructions that operate on data outside the processor, for example, conditional branch instructions, typically suffer from increased latency. The latency results from the time interval it takes the processor to obtain the data and to operate on them to execute the instructions. Typically, a source outside the processor interrupts the processor. In response, the processor uses an interrupt service routine to obtain the data from the outside source, and executes the instruction or instructions that operate on the data. The period from the initial interrupt to the execution of the instruction within the processor often takes many clock cycles. The interrupt-driven scheme results in reduced system performance because of the increased latency. Thus, a need exists for improved latency in the data-processing system when it executes instructions that operate on data residing outside the processor circuitry.
One aspect of this invention contemplates apparatus for improving latency in data-processing systems. In one embodiment, a configurable integrated-circuit device according to the invention includes a plurality of regions and a common circuitry. Each of the plurality of regions of the integrated-circuit device includes configurable electronic circuitry. The common circuitry provides at least one signal to at least two regions of the plurality of regions. The common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions. A data-processing system according to the invention includes the configurable integrated-circuit device and at least one peripheral circuitry coupled to the configurable integrated-circuit device.
In another embodiment, a configurable integrated-circuit device according to the invention includes a plurality of regions that each include electronic circuitry, and a common circuitry. The common circuitry provides at least one signal to at least two regions of the plurality of regions. The common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so that the latencies of the at least one signal to each of the at least two regions tend to be equalized. A data-processing system according to the invention includes the configurable integrated-circuit device and at least one peripheral circuitry coupled to the configurable integrated-circuit device.
In a third embodiment, a programmable logic device (PLD) according to the invention includes a plurality of regions that each include configurable electronic circuitry, and bus circuitry that couples to the plurality of regions. The PLD also includes common circuitry that couples to the bus circuitry. The common circuitry provides a signal to the plurality of regions through the bus circuitry. The common circuitry and the plurality of regions are positioned within the PLD so as to improve the latencies of the signal to each region. A data-processing system according to the invention includes the PLD and at least one peripheral circuitry coupled to the PLD.
Another aspect of the invention contemplates methods for improving latency in data-processing systems. In a first embodiment, a method according to the invention for improving latency in a configurable integrated-circuit device includes providing the configurable integrated-circuit device, and partitioning the configurable integrated-circuit device into a plurality of regions that each include configurable electronic circuitry. The method also includes within the integrated-circuit device a common circuitry that provides at least one signal to at least two regions of the plurality of regions. The method positions the common circuitry and the at least two regions within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.
In a second embodiment, a method according to the invention for improving latency in a configurable integrated-circuit device includes providing the configurable integrated-circuit device, and partitioning the configurable integrated-circuit device into a plurality of regions that each include configurable electronic circuitry. The method also includes within the configurable integrated-circuit device a common circuitry that provides at least one signal to at least two regions of the plurality of regions. The method positions the common circuitry and the at least two regions within the configurable integrated-circuit device so that the latencies of the at least one signal to each of the at least two regions tend to be equalized.